IBM 000-002 : IBM Tivoli Storage Productivity Center V4.1 Implementation Exam

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IBM V4.1 guide

Simultaneous Exploration of power, genuine Design and Architectural performance Dimensions of the SoC Design area using SEAS | 000-002 exam dumps and Real exam Questions

Nagu Dhanwada1, Reinaldo Bergamaschi2, William Dungan1, Indira Nair2, William Dougherty1, Youngsoo Shin3, Subhrajit Bhattacharya2, Ing-Chao Lin, John Darringer2, Sarala Paliwa1l1 IBM digital Design Automation, 2070 Route 52, MS 2A1, Hopewell Jct, ny 12533, USA2 IBM T.J. Watson analysis center, Yorktown Heights, the big apple, USA3 Korea superior Institute of Science and technology, Daejon, KoreaContact: Nagu Dhanwada, Tel: 1-845-892-4359

summary :

SEAS – SoC Early analysis and Design system became brought in [1]. The leading aim in the back of SEAS changed into to provide early design comments when it comes to the quite a lot of facets like power, architectural performance, floorplan / die-measurement of core-primarily based SoCs to the equipment architect, whereas keeping the hyperlinks to implementation. in this paper we discuss extensions to SEAS in the areas of physically-mindful power optimization via voltage island physical planning, transaction stage practical simulation platform for embedded software building, and a transaction degree energy analysis methodology for early power estimation. We additionally latest how simultaneous exploration of vigor, physical design and efficiency elements of a SoC may also be performed within SEAS.

SEAS Overview

SEAS allows users to easily specify a design in a block-diagram-like description and run sorts of analyses which might consistently be unimaginable to do early in the design process with proper accuracy. These analyses include performance, floorplanning, timing and energy. SEAS can tackle core-primarily based SoC designs, where the cores can be found in a library, together with characterization records and models (e.g., for performance evaluation simulation). The forms of models needed might be described in the following sections.

The main capabilities of SEAS from a consumer point of view is the means to explain measure and alter the specification at a extremely high-stage of abstraction and promptly evaluate the results in performance, enviornment, timing and vigour. If the results are not satisfactory, the dressmaker can promptly trade the structure, the floorplan, or the cores being used and run the analyses again. determine 1 illustrates the usual organization of SEAS. The individual analyses algorithms don't seem to be necessarily novel, despite the fact they needed to be adapted and tuned to the design illustration getting used (block-diagram). This tuning is essential to the accuracy of the effects.

As illustrated in figure 1, SEAS includes of an enter description comparable to a block diagram and diverse analyses engines. each and every engine has its own set of algorithms and interior model derived from the initial block diagram, and makes use of characterization facts and models for the cores attainable from a core library. besides the analyses engines, the netlist era portion of SEAS, translates the block diagram description and the gadget configuration assistance into an RTL description together with the set of cores and the vital glue logic enforcing the SoC. This RTL description together with the set of constraints from the analyses engines can be taken via an RTL-GDSII movement to complete the hardware implementation of the SoC.

figure 1 : SoC Early evaluation gadget

Use situation for vigor-performance-actual design tradeoff analysis in SEAS

in this area we current a use situation regarding how vigor connected architectural optimizations can be carried out inside SEAS. in the leisure of the paper the individual components of SEAS that allow these optimizations are discussed. the following could be a set of steps that can be performed via an SoC dressmaker using SEAS, 

  • construct block diagram (virtual design) for the simple SoC.
  • Map to purposeful Transaction stage mannequin (TLM) / efficiency based TLM view to generate a systemC description of the SoC
  • define a workload to model the application software or use the genuine utility utility, execute systemC simulation and acquire architecture performance suggestions (latency, throughput, aid utilizations, and so on) for the SoC
  • Map to an influence view of the SoC, and acquire vigour evaluation results. This step would be done via enabling the power evaluation mode when executing the systemC efficiency/practical TLM simulation
  • Use the outcomes from energy and architectural performance evaluation, and discover distinctive vigour connected optimizations within the SEAS atmosphere. These may also be application optimizations in addition to changes to the chip physical architecture by executing distinctive parts of the SoC at distinctive voltages, as a consequence exploring vigor-efficiency tradefoffs for the SoC being designed.
  • discover and validate architecture power optimizations in a genuine design context, the usage of the set of possible compatibility relationships decided within the steps of architectural efficiency and vigour simulation, through the use of voltage island genuine planning element in SEAS.
  • feedback latency advice of the voltage island partitioning solutions to the architectural performance models, in order that the dressmaker can have an idea of the efficiency tradeoff it truly is being made to obtain a specific low vigour design solution for the SoC.
  • If performance is convinced, use the netlist era parts of SEAS to create the precise-degree exact RTL for the SoC, and use floorplan and voltage island answer generated within the voltage island physical planning step as preliminary constraints going right into a RTL-GDSII design movement.
  • all of the mapping steps are automatic in SEAS, the feedback from evaluation effects of a specific step to an different one is enabled through parameters and is supplied through the integrated ambiance. The clothier has the potential to constrain and handle facets of the design within SEAS. leisure of the paper discusses some of these key materials.

    Transaction degree simulation platform for PPC/CoreConnect structure analysis

    Transaction level fashions and simulation systems composed of such models for IP cores are more and more getting used for the intention of SoC structure evaluation and early embedded utility construction. These are gaining extra relevance with rising common structure modeling languages like systemC. using the IBM CoreConnect SystemC Modeling environment that forms part of SEAS, designers can put collectively SystemC fashions for finished systems including PowerPC processors, CoreConnect bus structures, and peripherals. These models may well be simulated using the ordinary OSCI (Open SystemC Initiative) SystemC runtime libraries [4]. Our models and atmosphere deliver designers with a gadget simulation/verification capability with the following qualities:

  • Simulate precise software application interacting with fashions for IP cores and the ambiance for full gadget purposeful and timing verification, probably under actual-time constraints
  • investigate core interconnections and communications via buses and other channels
  • Inter-core conversation have to be cycle-approximate, which means cycle-approximate protocol modeling
  • verify that equipment supports sufficient bandwidth and concurrency for target purposes
  • Simulation performance is ample to run a big utility application with an working equipment booted on the gadget
  • Transactions are modeled as happening over conversation channels
  • Computation (interior a core) can also not be modeled on a cycle-with the aid of-cycle groundwork, so long as the input-output delays are cycle-approximate
  • The processor mannequin doesn't need to be a real architectural mannequin; a application-based guideline Set Simulator (ISS) with adequate performance and timing accuracy is used,
  • For the situation where utility software does not exist, the ambiance provides facilities to model the software behavior on a processor via a everyday processor model inside which utility habits can be precise via a scripting interface,
  • to be able to simulate precise software, including the initialization and inner register programming, the models must be "bit-true" and register correct, from an API point of view. The models have to supply APIs to permit programming of registers as if the user have been programming the genuine hardware device,
  • models don't need to be a specific architectural illustration of the hardware. They can be behavioral models so long as they are cycle-approximate representations of the hardware for the transactions of activity (i.e., the genuine transactions being modeled).
  • All models have to be "macro-synchronized" with one or extra clocks. This potential that for the atomic transactions being modeled, the transaction boundaries (begin and conclusion) are synchronized with the applicable clock.
  • A gadget detailed on the block diagram stage of abstraction in SEAS, could be maped to  a TLM view that has some of the above mentioned traits and a systemC simulation may also be executed on this TLM view of the SoC.

    Transaction level power modeling

    power is becoming an incredible difficulty in SoC Design, and the want for tackling it early on in the design cycle is imperative for chip designs. central to transaction stage energy analysis is a power modeling methodology for IP cores constituting the system. to move together with the Transaction level fashions for the IP cores, we're setting up a transaction degree power evaluation methodology in SEAS to permit early power estimation, which is in brief described during this part.  The common methodology is as follows:

  • establish initiatives or guidelines from the core description,
  • signify energy consumption of every task or guideline from low-degree implementation,
  • Generate vectors corresponding to these directions or tasks executing on the certain IP core
  • place, route, extract parasitics for the cores
  • Use energy simulation tools with the parasitics, to generate energy characterization assistance for these directions or projects,
  • Create macromodels according to a lot of IP core parameters:
  • Parameters may also be bit-width, switching exercise of records, buffer size
  • increase the TLM to extract the parameters for macromodel
  • This can also be achieved dynamically at run-time to derive advice all through simulation (tradeoff between simulation accuracy and speed should be taken into account)
  • regular TLMs trap the functional initiatives linked to the conduct of an IP Core, but would not always comprise loads of the non-purposeful initiatives related to the core. These non-purposeful initiatives would be fairly crucial from a power consumption point of view. due to the fact that TLMs are not customarily developed with the view of taking pictures all of the vigour related initiatives, this ends up in a different difficulty of desiring to having a mapping mechanism from the set of initiatives (useful and non-useful) recognized all the way through the transaction degree energy characterization formula to the set of tasks latest in the existing transaction stage mannequin.  here's one of the most interesting elements of the transaction stage vigor modeling employed in SEAS. An example is proven right here for a reminiscence controller core:
  • useful projects – read, write, initialize
  • non-functional projects – single bank refresh, multi-bank refresh, energy control
  • parameters for useful task
  • tackle sequence, information switching activity, burst linked parameters,
  • The mapping can be carried out statically or dynamically, and kinds the transaction level vigor estimation component of SEAS which is at present being developed. the usage of the transaction level power and efficiency simulation the user can get early structure efficiency and vigor estimates for a given utility that's executing. The next area discusses how the genuine cognizance of vigour connected structure modifications will also be made inside the identical SEAS ambiance by using voltage island physical planning capabilities.

    Linking vigor and physical design: genuine Planning of Voltage Islands for vigor optimization

    Voltage Island [3] is a method, which is effective in reducing each the switching and standby add-ons of vigor consumption in a design. A voltage island is a gaggle of on-chip circuit elements powered with the aid of the equal voltage supply, unbiased from chip-stage voltage, which allow execution of different parts of design at diverse voltages to optimize energy. In an SoC context, this makes it possible for core-level energy optimization with the aid of making use of a power deliver this is pleasing from the rest of the design. here's an additional dimension that can be explored early on within the SoC design method. When taking into consideration architectural vigor optimizations in the SEAS environment, the designer can evaluate the genuine recognition of such energy connected choices by using the voltage island planning portion of SEAS.

    An SoC dressmaker trying to construct a low energy SoC making use of Voltage Island points will be faced with choices like,

  • what is a great partition of the design into distinctive areas and what types of voltages are assigned to these regions,
  • a way to generate an early physical design implementation/floorplan for such a voltage island answer with the intention to estimate the effort involved in realizing the physical design of such options
  • Early physical design for core primarily based voltage island options is quite a complicated task in itself. here's because of the interaction between projects like vigour grid routing, static timing, floorplanning, and placement. The complexity of this project grows with the variety of islands and must be taken into consideration when performing vigor linked architectural optimizations. therefore, a fashion designer the usage of voltage islands would need to neighborhood cores powered by means of the same voltage source and confirm that the grouping doesn't violate different design metrics equivalent to timing and wiring congestion. also Voltage islands should be placed close to energy pins to minimize vigor routing complexity and IR drop. considering every island requires its own vigor grid and level converters to speak to distinct islands, the overhead in view of area and prolong is crucial. These extra necessities lend themselves as a different and complicated physical planning issue. These tasks can't be carried out manually and there's obviously a necessity for an automated answer for this problem of voltage island design for core based mostly SoCs.

    developing voltage islands in a chip design as a way to optimize the typical vigour consumption, contains voltage island partition era, voltage degree project and floorplanning. The leading approach in SEAS for voltage island planning incorporates bodily aware voltage island partitioning and a technique for solving the difficulty of performing simultaneous voltage island partitioning, level task. The technique agencies diverse cores into voltage island partitions whereas choosing a floorplan for the chip and the particular person islands. The overall method for physical planning latest in SEAS carries: a) characterizing cores in terms of voltages and vigour consumption values; b) offering a group of IP cores that belong to a single voltage island RLM (Random logic Macro); and c) assigning voltages for the voltage island RLMs, all in the context of generating a bodily realizable floorplan for the design. This algorithm [2] is in response to a chain-pair- simulated annealing method that employs a compatibility graph structure for retaining the voltage, physical design compatibility relationships between the cores of the SoC. The ensuing voltage island partitioning and floorplan answer can be used to augment the latency information again into the architectural TLMs, and also can be used as an preliminary answer for the chip implementation process.

    determine 2: efficiency and vigor analysis results for 1-EMAC and a couple of-EMAC designs (determine at the beginning published by way of the authors in [1], reused with permission from © ACM)

    Design illustration

    in this part we discuss a PowerPC 405/coreconnect primarily based packet processor design, for instance some of the components of SEAS. The design includes of an Ethernet sub-equipment represented by the Ethernet controller (EMAC), a Media entry Layer (MAL) core, get hold of and transmit FIFOs. It also carries a excessive-velocity memory controller (HSMC), an exterior bus controller (EBC), DMA controller, Interrupt controller and a variety of peripherals together with 2 UARTs, 1 IIC and 1 timer. The cores are all connected to either the excessive-velocity Processor native Bus (PLB), or the On-Chip Peripheral Bus (OPB).

    The design become created at the virual design of abstraction and the experiment incorporates evaluating this design for Ethernet packet processing purposes. efficiency analysis can be used for measuring the system throughput and CPU utilization, after which the architecture can be changed by means of adding a 2d Ethernet controller and the performance analysis repeated. The floorplan for each designs may be generated and die sizes estimated, together with wire size and vigour advice.

    The cores concerned in packet processing are the EMAC, MAL, PLB Arbiter, CPU, and HSMC. The packets arrive from the community to the EMAC input and are received into it’s receive buffer. The MAL works as a dedicated DMA and transfers the packet during the PLB bus, to the memory controller and eventually into an external memory. The time it takes for receiving a packet into memory depends on the data fee, the dimension of the packet, the skill of the MAL (dimension of burst transfer, variety of bursts mandatory per packet) and a few consistent delays linked to the EMAC and HSMC. After the packet is acquired in reminiscence, the CPU then strategies it by studying the header, computing a brand new handle and writing returned a new header. in this example, it is thought that this CPU header processing is constant and does not depend upon the size of the packet. This CPU time is measured off-line through profiling thoughts. The packet is then examine via the MAL and transmitted, throughout the EMAC, returned to the community.

    device throughput and CPU utilization are shown in determine 4 for distinct packet sizes. Throughput depends on variety of packets, size, processing skill, and is limited via the maximum channel potential (highest bits that may also be transmitted through EMAC in a second). The ratio of busy to idle instances of CPU is observed because the CPU utilization. With small packets and 1 EMAC, the CPU is 100% busy and throughput increases with packet size, up to the maximum allowed by the channel. during this instance the EMAC is restricted to 100 Mbits/sec. Above a undeniable packet measurement, throughput is restricted to 100Mbits/sec, which motives the CPU to develop into idle as packet obtain times turn into more advantageous than CPU processing time. To boost throughput past 100Mbits/sec, the leading option is to add further EMACs to the design. adding one extra EMAC doubles the highest throughput to 200Mbits/sec allowing larger costs, and greater packets.

    To account for the opportunity of different potential projects that can be carried out by means of the gadget, we might target a utilization percent of around eighty% as a substitute of concentrated on a 100% utilization. this might provide some leverage for the CPU to respond to different equipment requests. This instance demonstrates the skill in SEAS to change the structure to fulfill the requirements and directly validate structure performance using efficiency evaluation.

    vigour evaluation is run with the performance simulation. determine 4 shows the vigour consumed with the aid of the gadget throughout packet processing for both digital designs. It will also be seen that vigor does not raise vastly within the 2-EMAC case, which is anticipated considering the fact that lots of the vigor is dissipated through the CPU when lively. It also indicates that when the CPU becomes partly idle the energy decreases accordingly. This simulation assumes that the EMAC, MAL and CPU might be active when in use, and idle in any other case, and all other cores are in sleep mode.

    Given these two architectural design aspects, they now deserve to be evaluated for measurement and timing. We generated the floorplan for each virtual designs and estimated their required die sizes. according to floorplan area by myself, the 1 EMAC version fit right into a 5.57x5.57mm photograph, and a pair of EMAC edition essential a 6.05x6.05mm photo. on account of pin-obstacles on the 5.57mm image, the 6.05 mm picture changed into used for both the 1-EMAC and 2EMAC versions. each of those floorplans supply a place to begin for vigour optimization the usage of the voltage island physical planner. SEAS benefit in this case of performing a floorplanning and genuine design analysis  was to display that the higher efficiency design (2 EMACs) could slot in the equal die size, with the equal silicon cost.

    If aggressive vigour administration is needed for the SoC, then parts of the design can be finished at distinctive voltages. An early view of the influence and vigour mark downs attainable by way of voltage islands is pondered using the voltage island planning engine of SEAS. during this scan we used the 1-EMAC and a pair of-EMAC versions of the SoC design instance and the initial floorplan for the digital design because the beginning point for the voltage island genuine planner. The purpose here is to get a concept of the overhead incurred (area, performance, ) and the conceivable vigour mark downs by way of voltage island based mostly energy optimization concepts.

    An preliminary floorplan for 2EMAC version is proven in figure 3. This was generated due to the fact that pre-placement, chip IO constraints and with wirelength, overlaps  as the fundamental aims for the applications of die-size estimation. The packing containers the place the mobile names are given (CPU, EMC1, and so on) point out pre-positioned cores which aren't to be moved during planning; during this scan, all cores are assumed to function at a single 1.3V provide within the preliminary design. For Voltage Island planning, we assign prison voltages inside a spread 1.0V to 1.3V for every core.

    figure 3 : preliminary floorplan for 2EMAC Design with single Vdd=1.3V

    In determine four(a) of the example, an answer became generated with the constraint on total number of voltage islands set to three. each EMC1 and HSMC will also be between [1.1-1.3], and CPU at 1.3V.

    For this case, three voltage islands are created by means of the planner: two are shown with enclosing rectangles both with 1.1V supply, and the third one inclusive of a single core (EMC1) is powered through 1.0V. observe that HSMC remains at 1.3V youngsters its minimum legal voltage is 1.0V. It may well be operated at 1.1V instead of 1.3V whether it is protected in the voltage island on the left-hand facet of the photograph, however that could result in a significant dead space within the voltage island considering the fact that EMC0 has a hard and fast area. EMC0 is powered with 1.1V, which is the deliver of the enclosing voltage island, even though it’s minimal felony voltage is 1.0V, whereas RX0 is at its minimum deliver. For this solution instance, the vigor discount rates finished via the voltage island planning is sixteen.9% while the enviornment overhead is only 8.3%.

    figure 4 : Voltage Island Planning for 2EMAC

    determine 4(b), suggests the effect of Voltage Island planning the same design with a constraint of 4 voltage islands. The generated islands are proven as shaded areas with the corresponding voltage levels. This answer has a neighborhood overhead of seven.7% and a power discount rates of 17.four% respectively when in comparison to the initial answer. The latency enhance because of islands can be factored again into the structure performance analysis step with a purpose to get a comments on the efficiency affect additionally. the usage of these kinds of analysis (efficiency, power and area) and exploration engines in SEAS, an SoC Architect can tune the equipment structure. The outcomes of analyses may also be carried forward into the relaxation of the design system by using the netlist generation component of SEAS, which would generate a accurate degree netlist from the digital design that may also be taken through RTL—GDSII design flows.Conclusion

    This paper offered use eventualities of vigor-performance-actual design tradeoff analysis  within a SoC early analysis gadget: SEAS, and discussed its materials that allow such eventualities. The presence of diverse analysis capabilities inside an built-in environment helps designers make these early architectural selections while considering the fact that the genuine realization of the specific SoC. The merits of the strategy consist of: (1) an easy block-diagram-like notation for design specification which permits the fashion designer to enter and adjust the design without delay, (2) built-in analyses algorithms for efficiency, floorplan, timing and vigour, which permit the fashion designer to trade the architecture, the core option or the floorplan of the design and immediately consider the effect on different domains. The ideas introduced have been tried on real designs and outcomes have proven that estimations in response to our strategy will also be correct sufficient to e-book early design decisions in addition to used via reduce-level equipment. The capacity to explore distinctive features of an SoC architecture within the context of realizing its genuine implementation in an built-in atmosphere offers a magnificent system-on-a chip analysis and design skill.


    1.    “SEAS: A equipment for Early analysis of SoCs”, R. A. Bergamaschi, Y. Shin, N. Dhanwada, S. Bhattacharya, W E. Dougherty, I. Nair, J. Darringer, S.  Paliwal, complaints of CODES/ISSS 2003.

    2.    “Architecting Voltage Islands in Core-based gadget-on-Chip Designs”, J. Hu, Y. Shin, N. Dhanwada, R. Marculescu, proceedings of international Symposium on Low power Electronics and Design 2004.

    3.    “Managing vigour and efficiency for gadget-on-Chip designs the use of voltage islands,” “D. E. Lackey, P. S. Zuchowski, T. R. Bednar, D.W. Stout, S.W. Gould, and J .M. Cohn in Proc. Int’l Conf. on computer Aided Design, Nov. 2002, pp. 195–202,

    4.    “”

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