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IBM V5.2 answers

IP Processor Core Platform option in accordance with SoC architecture: a case examine | 000-872 Latest courses and exam Questions

by way of Aoudni Yassine, GMS/LESTER LaboratoriesSfax/Lorient, Tunisia/France

abstract:

This work aims to examine a number of IP core processor primarily based structures in response to here key parameters: FPGA architecture, coprocessor and accelerator integration, RTOS and HW-SW refinement equipment. These key parameters are required to choose a flexible and excessive performance IP processor core (and the associated tools) with the intention to implement a good monoprocessor PACM (Processor – Accelerator – Coprocessor – reminiscence) structure mannequin. A case examine for the PACM architecture model has been focused with a purpose to validate our key parameters. four IP processor cores were candidate to put in force the PACM structure model. at last, the selected ones corresponds to the Nios smooth processor core inside its development package (Quartus, SOPC Builder and STRATIX machine) and a shading algorithm for 3D photo remedy changed into carried out to prove the IP processor core platform adequacy with our PACM architecture mannequin.

1. Introduction

The designs of SoC in many utility domains are sometimes subject to stringent necessities when it comes to processing efficiency and flexibility [1]. To enable flexible competitively priced designs in a short design cycle, emerging designs are in line with hardware/software SoC platforms that combine diverse processor cores as programmable supplies along side dedicated hardware (HW) accelerators inside a single economical chip. Programmability is added in these single-chip architectures (consequently offering the preferred flexibility in the design), while maintaining many of the advantages of custom-made VLSI options (such because the competencies to optimize the processing performance and vigor dissipation) [2].

Hardware/utility co-design formula exists nowadays for designing the distinct hardware and application substances of a SoC structure [3]. As time to market pressures and product complexities climb, the need to reuse complicated constructing (also called intellectual Property (IP) or virtual part (VC)) also increases. These components characterize processor architectures (RISC, SPARC…) and functions for selected domain like signal processing (DCT, FFT), telecommunication and multimedia (VLC, faster codes) and so forth. during this area, SoC implementation administration requires a robust codesign atmosphere with a purpose to master the complexity and the diverse refinement steps of the system from a high stage specification.

counting on the software, different utility-specific architectures using diverse execution models and combinations of software and hardware components may well be required (e.g. driven by programmability, efficiency, and vigour computing necessities). Even the option of the programmable processor to make use of is closely dependent on the software. briefly, the question to reply is: can the identical IP processor core prototyping systems [4] tackle all structure fashions or is there a trade-off between these  systems and structure fashions? in this paper we propose an answer and exhibit it the use of our case examine.

figure 1: SoC structure mannequin in response to a processor core

A classical mono-processor SoC architecture model is depicted in figure 1. here's the mannequin we have selected to put into effect the PACM (Processor – Accelerator – Coprocessor – reminiscence) architecture model as might be explained in the following.

This paper items a case look at comparison of a few IP processor cores prototyping platforms to opt for the relevant ones for the goal architecture (see determine 1). in the beginning, we present the comparative analyze between IP processor cores based platforms and the important thing parameters of alternative extracted from the PACM structure model. A 3D shading algorithm instance has been carried out to demonstrate the IP processor core platform adequacy with our PACM architecture mannequin. finally, we conclusion with conclusion.

2. IP processor core platform for the PACM architecture model

during this part, for the architecture presented in figure 2 and in accordance with the mannequin offered in determine 1, we show that several IP processor cores platforms, similar in first view, don't latest the identical adequacy degree with the centered model of execution. The determine 3 items the PACM model. in fact our structure is built round a processor core (as an example Nios, ARM, LEON…) which presents configuration alternatives for including coprocessors reached during the leading processor registers (as an instance floating factor unit, HW divider, HW mathematic features ...).

figure 2: PACM structure

The processor communicates with committed HW accelerators via a typical on chip HW/SW bus (e.g. Amba, Avalon, IBM CoreConnect…) the usage of control logic and particular reminiscence blocks.

Coprocessors and HW accelerators usage depends upon the utility complexity and on the computing constraint requirements. so as to supply greater flexibility and adaptableness to the SoC, we have chosen the reconfigurable technology to put into effect our SoC.

If we analyze the important thing parameters of the PACM structure model, the satisfactory IP processor core platform ought to integrate right here facets:

  • The IP core processor must be implemented within FPGA device characterized by way of a heterogeneous architecture (common sense features, DSP blocks, RAM blocks, I/O pin…) and by means of a measurement capable of integrate the HW and SW ingredients of the SoC.
  • The IP processor core ought to offers opportunities to integrate some coprocessors within its ALU and reached through the processor main registers to get an ASIP model [5].
  • The IP processor core and HW accelerators need to be linked via an on chip HW/SW bus or other on chip HW/SW verbal exchange module [6].
  • RTOS alternative with the corresponding port to the targeted IP processor core should be current [7].
  • The HW and SW refinement equipment ought to be powerful and effective to restrict the time-to-market constraint [8].
  • All these key parameters correspond to the standards to select a suitable IP processor core platform. We made a qualitative examine for distinct consultant IP processor core platforms, and consider their adequacy with the PACM architecture model.

    desk 1 : IP processor core structures comparaison

    We performed an experimental analyze in keeping with the main aspects of IP processor core systems. The consequences are introduced in table 1. We notice that all presented IP processor core platforms supply a robust and effective HW and SW refinement equipment like ISE Xilinx tool and Quartus, on chip HW/SW bus as AMBA (LEON and ARM Excalibur kits) and IBM CoreConnect (PowerPC and Microblaze kits) and additionally a port for a lot of RTOS like RTEMS port on LEON and ARM, WindRiver port on PowerPC and Microblaze, and so forth. besides the fact that children, handiest Nios, ARM and LEON IP cores can guide coprocessor feature. in addition, coprocessor integration in Nios and ARM IP cores is more speedy and versatile the use of the virtualization and customized guide era given via SOPC Builder consumer-buddy tool. additionally, Nios SoC can be implemented in massive STRATIX family unit [9] which consists of DSP blocks and diverse sizes of RAM blocks, unlike ARM building kit which is limited to APEX device and its core is a hard IP and never a soft one like the Nios core. consequently, we notice that the SoC platform in keeping with Nios IP processor core [10] supplied with Quartus and SOPC Builder environments through Altera [11] is probably the most appropriate to design a reconfigurable SoC according to IP processor core the use of the PACM architecture mannequin. certainly, SOPC Builder tool offers the dressmaker a virtual photograph of the Nios processor tender core and the accelerators can be linked to the Nios processor core throughout the Avalon on chip bus. custom directions are additionally provided with this platform with a view to facilitate the coprocessors integration within the Nios ALU. specifically, our alternative is in response to this ultimate characteristic in an effort to put in force a reconfigurable ASIP core.

    As a conclusion of this evaluation we are able to see that the available IP processor cores platforms can't tackle the entire SoC architecture fashions and that a analyze should be executed with a purpose to choose the correct IP processor core platform for the appropriate architecture mannequin. In our case the Nios processor core kit is suitable to the PACM architecture model.

    within the next section, as an example the efficiency of the use of the Nios processor core kit to put in force the PACM architecture model we existing a case look at on shading algorithms for 3D image remedy. Our platform consists of Quartus and SOPC Builder environments, Nios gentle core processor, an EP1S40 STRATIX gadget and the MicroC/OS-II RTOS [12]. observe that the RTOS implementation can be done in future work.

    3. Experimentation case examine

    during this case examine, we have carried out two 3D shading algorithms utilized in graphic synthesis: LAMBERT and GOURAUD [13]. These algorithms consist to cut an object in a number of polygons after which to assess the intensity of the gentle in each polygon of the thing. a number of mathematic expressions and vectors analysis have to be completed in order to get a light depth value for one polygon. The basic operations of these computing operations are the addition, subtraction, multiplication and square root. certainly, for each polygon we should calculate the enviornment commonplace vector, gentle route vector and the attitude between these two vectors. The difference between both algorithms is that GOURAUD takes under consideration the continuity between neighbours polygons in contrast to LAMBERT (see figure 3a and 3b).

    LAMBERT and GOURAUD algorithms can be applied in the Nios as a SW application. but to be able to accelerate the execution an answer consists to use HW accelerators. another solution can also be executed by extracting coprocessors from the SW execution with a view to speedup some vital components of

    figure 3a: shading with LAMBERT algorithm

    figure 3b: shading with GOURAUD algorithm

    the code. In commonplace these vital parts correspond to nested loop body operations which are finished a big number of time. These two sorts of implementation are presented in here paragraphs correct after the whole SW algorithms implementation.

    initially, we implemented these two algorithms as two accelerators linked to the Avalon on chip bus. certainly in the Quartus atmosphere, we can design a HW accelerator the use of a Block Design File (BDF) as introduced in determine 4, then we will generate the certain VHDL or Verilog code and finally we can run the compilation to simulate and to get the bit flow file. The BDF feature in Quartus atmosphere helps the clothier to get a appropriate HDL code in much less time with optimized components offered inside the vendor library. we now have used the PIO interface characteristic in SOPC Builder to link the HW accelerators with the Avalon bus. This tool is in a position to generate instantly the interface between the HW and the SW accessories this is positive to in the reduction of the HW/SW SoC time design.

    figure four: LAMBERT and GOURAUD Block Design data

    Secondly, we integrated mathematic coprocessors as customized instructions in the Nios soft core. in this case, the virtual design entry of the Nios in SOPC Builder is very helpful and effective to configure the processor core, specifically for adding either sixteen or 32 bits coprocessors by means of two leading ALU registers. the important thing element during this feature is the generation of certain coprocessor custom instruction standard through the Nios C compiler.

    table 2: effects obtained for the LAMBERT and GOURAUD algorithms

    table 2 offers the consequences obtained for the LAMBERT and GOURAUD algorithms the use of the accelerators and the coprocessors. The consequences are given in time period of required good judgment elements and in time period of execution time speedup compared to a full software implementation the use of the Nios. we will be aware that the speedup got the usage of GOURAUD accelerator is greater critical than the coprocessor one, nevertheless it wants more enviornment (i.e. FPGA supplies). on the other hand coprocessors LAMBERT implementation is greater benefit than accelerator ones when it comes to common sense cell and speedup. thus, the choice between accelerators or coprocessors implementation depends on the SoC execution time and FPGA substances constraints. observe that the use of this SoC platform a number of workdays are only needed for an exceptional implementation of these two complicated algorithms which prove the efficiency of the key parameters to choose a SoC platform for the PACM architecture model.

    four. Conclusion

    during this paper and in response to the PACM architecture model, we now have proven that the available IP processor cores structures cannot tackle all the SoC architecture fashions and an evaluation must be accomplished to choose the suitable IP processor core platform for the acceptable structure model. the important thing parameters that we have regarded to choose the correct IP processor core platform are right here ones: FPGA structure, coprocessor and accelerator integration, RTOS and HW-SW refinement equipment in line with these parameters a platform according to the Nios STRATIX construction package was chosen to enforce the PACM architecture mannequin. To validate our alternative two 3D shading algorithms have been implemented on the Nios platform using the Quartus and SOPC Builder. consequences have validated the merits using such platform for the PACM architecture mannequin. In future work, we propose to put into effect the RTOS subroutine and to analyze the SoC energy performance for the PACM architecture with video compression algorithms.

    References

    [1] Julio C, B.Mattos, Luigi Carro, effective architecture for FPGA-primarily based microcontrollers, ISCAS paper number 2825, 2002.

    [2] Amit Singh, Malgorazta Marker-Sadowska, effective circuit clustering for area and power discount in FPGAs, SIGDA 2002.

    [3] invoice Lin, Karl Van Rompaey, Stenven Vercauteren, Designing single chip programs, ASIC 1996.

    [4] M. Bolado1, H. Posadas1and All, Platform in keeping with Open-source Cores for Industrial purposes, Design Automation and look at various in Europe February sixteen-20, Paris DATE’2004.

    [5] F. Campi, A. Cappelli,A. La Rosa, L. Lavagno,R. Canegallo, A Reconfigurable Processor structure and utility building atmosphere for Embedded programs, Reconfigurable architecture Workshop, quality France uncooked’2003.

    [6] Vesa Lahtinen, Kimmo Kuusilinna, Tero Kangas, Timo Hamalainen, Interconnection scheme for continual-media methods-on-chip, pages 123-138 Microprocessors and Microsystems 26, 2002.

    [7] V. Nollet, P. Coene, D. Verkest, S. Vernalde, R. Lauwereins, Designing an working gadget for a Heterogeneous Reconfigurable SoC, Reconfigurable structure Workshop, excellent France uncooked’2003.

    [8] Y .Aoudni, I. Maalej and al., evaluation of tough ware/utility gadget on Chip: Case examine, IEEE4. Conclusion


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