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Exam Name : Troubleshooting with Sniffer Portable/Sniffer Distributed
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A Platform-primarily based know-how for Fault-strong SoC Design | 1T6-510 cheat sheet and PDF Questions

Riccardo Mariani, YOGITECH SpASan Martino Ulmiano (PI) - ITALY

abstract :

When designing a system-On-Chip (SoC) for safetycritical or excessive-reliability applications, the design area that a gadget architect need to believe is reasonably significant as a result of the variety of faults that may affect the SoC, the diverse screw ups that these faults can generate and the large set of concepts that can be used to observe, confine or cease the ensuing hazards, each one with its efficiency and cost. in this paper it is proposed a scientific platform-primarily based know-how, in which a library of reusable IPs (HW and SW) is used along with a collection of equipment and methodologies to discover the most desirable solution during this design area, following the IEC61508 guidelines.

Introduction

If we define ¡°robustness¡± as the ability to proceed the mission reliably despite the existence of systematic or random faults [1], we are able to say that up to date digital programs are less and less robust. here's as a result of the complexity of the brand new applied sciences, e.g. because of softerrors susceptibility, coupling results, leakage contribution and extended sensitivity to interior and exterior disturbs etc. things are made worse by way of the fact that at the present time deep-sub micron technologies and multi-CPUs digital systems are utilized in high extent purposes the place safety is a key ingredient: in car business, digital systems are involved in airbags, active brakes, engine handle and future x-bywire automobiles. In such state of affairs, there's more and more the want of tools, methodologies and HW/SW architectures with which engineers can manipulate robustness, safety and connected expenses at all of the distinctive level of abstractions.

overseas norms exist to outline requirements for protection, such the IEC 61508 for useful defense of electrical/electronic/programmable electronic safetyrelated systems [2]. in spite of the fact that these norms often confer with finished equipment and not to system-On-Chips, they also comprise specific instructions and necessities for the equipment subcomponents, together with CPUs, memory techniques, bus infrastructure and so forth. An extension of such norm to ASIC is likely to appear within the next months. one of the crucial simple ideas of IEC61508 is the definition of ¡°defense integrity level¡± (SIL), i.e. the discrete level (one out of a probable 4) for specifying the security integrity requirements of the protection functions to be allocated to the safeguard-linked programs, where defense integrity stage 4 has the optimum degree of safety integrity and defense integrity level 1 has the lowest. standard methods for automobile require a SIL2 or SIL3 safeguard integrity level.an important position is performed by means of the ¡°Beta component¡± i.e. the probability of standard trigger disasters that could become a limiting element above all when dissimilar, functionallyequal channels are applied in the equal silicon.

Three classical examples of processes for safeguard critical microcontroller are the Delphi SMA [3] and both Bosch mutual and asymmetric architectures [4]. inspecting them, on one side a dual-redundant answer can assure the preferred diagnostic coverage but it surely requires a major HW, SW and vigour overhead as also it lacks of range, i.e. lots of the diagnostic is accomplished with a 2d CPU equal to the first one, and hence it is vulnerable to normal-mode blunders. On the different aspect, at the moment accessible uneven options suffer of a low diagnostic insurance and a high SW overhead is required to compensate that. different options, such including fault detection and correction circuitry in the CPU itself or similar ones, are expensive in terms of CPU remodel and they violate a primary guiding principle of the IEC61508 that requires that the diagnostic common sense is evidently separated by means of the safeguard function itself. hence these intrusive strategies are greater relevant to enhance the CPU dependability than to enable the design of a safety-primary digital gadget. it is additionally value to word that many of the state-of-paintings innovations chiefly depend on SW to guarantee the essential diagnostic coverage for the different add-ons of the microcontroller (such memory subsystem, peripherals and bus infrastructure) and for this reason the SW building and qualification procedure drastically influences the ordinary costs, chiefly for almost all of those solutions that are poorly scalable and reusable.

Platform-based procedures [5] are commonly used to be a proven answer to this difficulty, considering that in time-honored they enable hardware and utility standardization, they're adaptable on the user¡¯s wants, they can generate clear codes & scripts in a smartly defined stream, they are quite simply linkable with the working device, they enable effortless verification of sub-blocks and they are upgradeable and scalable. For safety-critical or high-reliability purposes, the typical platform-based mostly strategy have to be enriched with the entire measures (HW and SW) that could assure, with the same quantity of high-quality, reusability and flexibility, the mandatory degree of protection integrity for the given utility: this is the mission of the know-how offered during this paper

A platform-based mostly expertise for fault robustness

in this paper it's proposed a platform-primarily based expertise ¡°faultRobust¡± (schematically represented in figure 1) composed with the aid of [6]:

  • a design and validation methodology in adherence with IEC 61508, together with FMEA and Fault Injection;
  • a flexible and configurable library of HW IPs complementing (wrapping) the SoC sub-techniques: each and every of those faultRobust IPs (fRIPs) will also be standalone or will also be combined with other fRIPs for a complete answer;
  • a tool suite in keeping with existing compilers to tackle the HW-SW integration and configuration circulate.
  • determine 1 : the proposed platform-based mostly know-how

    The design and validation methodology it is one of the key aspect. A tool suite extracts suggestions from the security necessities Specification (SRS, a doc required by using IEC 61508 to outline the protection dreams) and from the design database (RTL, gate-degree and lower back-conclusion netlists), by using scripts in response to commercially obtainable EDA tools. These facts are entered in a extremely specific Failure Mode and outcomes evaluation worksheet. Then, fault fashions and failure modes are regarded in adherence to IEC instructions. eventually, protected failure fraction (SFF) and diagnostic coverage are instantly computed the use of a statistics formula embedded within the FMEA worksheet.

    IEC 61508 particularly recommends that fault-modeling and fault-injection are intensively used during the design, verification and validation circulate. To be compliant with that, one more device suite performs a design-stage fault injection working both at lowest (transistor, gate) and at the highest (block) degree. it is a mix of a PERL/C primarily based tool and Specman by using Cadence. it is immediately linked to FMEA and it uses an operational profile based mostly algorithm, enhancing the pace of fault injection crusade. This fault injector isn't committed to selected fault models: it could deal with different fault models, such transient faults, everlasting faults, mixture of the twos and customised fault fashions (they are modelled the use of the IEEE1647 ¡°e¡± language).

    The insurance policy of memory sub-programs

    Embedded memories (Static, Dynamic RAMs and Non risky memories) are nevertheless probably the most vital blocks regarding reliability, dependability and protection. existing solutions have many limits, such as no adherence to specific defense norms; entry time overhead as a result of the coder/decoders in the information course; reminiscence area overhead as a result of the codes, in selected for Error Correction Codes (ECCs); insurance policy degradation as a result of numerous blunders; and low configurability. For SW faults, reminiscence insurance plan (MPU) innovations are used however they're CPUcentric and they don¡¯t offer an entire insurance plan at equipment level, particularly for multi-master systems on chip.

    The proposed platform-primarily based technology includes a configurable and re-usable IP for protection of reminiscence sub-methods (fRMEM), based on a outdated work [7]. besides the use of ECC optimized for enviornment, power and assorted blunders detection probability, it adds proprietary concepts such as the implementation of measures to fulfil the requirements of IEC 61508, including a selfchecking structure for the supervisor itself; the ¡°fasttrack¡± choice enabling the maximum working frequency while retaining the identical stage of ECC protection and devoid of including wait cycles; the ¡°scrubbing¡± alternative to keep the coverage degree and reduce the Failure In Time (healthy), protecting the equal Hamming distance of the code and liberating the CPU to control these operations; the ¡°shared reminiscence¡± choice to permit the reduction of reminiscence code overhead as a result of ECC coverage, by means of storing codes in a separate reminiscence enabling partitioning of facts recollections in diverse pages with selectable protection degrees, by way of sharing the code memory between diverse data reminiscences and via enabling the reuse of code memory for data; the ¡°distributed MPU¡± alternative to allow a distributed memory coverage in multi-grasp architectures, checking if a reminiscence access with the aid of a given master fulfils rules such read/write permissions, person/privileged mode and the like.

    As represented within the determine 2, fRMEM consists of two blocks wrapping the memory controller and interfacing the memory. The Fault protection memory supervisor (F-MEM) block contains the entire alternate options concerning coding/decoding and other alternatives such fast-tune and scrubbing. The reminiscence Controller Extension (MCE) block extends the memory controller and it manages the way the bus interacts with the fRMEM, being responsible of services such MPU and so on. For Tightly Coupled reminiscences or records route reminiscences, lots of the services are finished by way of F-MEM. For non volatile reminiscences, codes can also be saved per observe or per page basis.

    main points of fRMEM are: a memory code overhead from 3% to 30% as a feature of coding scheme and use of the shared memory alternative; negligible entry time overhead with the quickly-track choice; Failure In Time (fit) reduce ingredient from 103 to 109 as a feature of coding scheme and use of the scrubbing option; gate count number between 1K and 6.5K gates counting on the configuration; ¡Ýninety nine% look at various coverage; ¡Ýninety nine% safe failure fraction (SIL3).

    figure 2 : the IP for protection of recollections

    The protection of CPU sub-methods

    Sparse good judgment criticality is expanding as smartly, certainly when deep-sub-micron or nanotechnologies are used. The fRCPU is an IP for insurance plan of a CPU sub-gadget. It isn't a replication of the CPU seeing that it's architecturally and functionally distinct and thanks to that it strongly reduces the Beta ingredient as required with the aid of IEC 61508. it is HW-centric, i.e. lots of the diagnostics are in HW: alarms are generated independently from the software and there isn't any efficiency have an impact on on CPU. It covers simplest what is truly significant to reach SIL3, allowing the minimum HW overhead (and energy consumption), the minimal connection necessities and complexity. In a few words, the fRCPU consists (see determine 3) of a CPU Sniffer Unit collecting, compating and coding signals from the CPU boundary, a Shadow Processing Unit executing the equal move of CPU, together with a register bank to keep a shadow cost of CPU main registers and a management unit to generate records/addresses. fRCPU compares its effects with the ones examine from CPU with a set of impartial checkers supervising the distinct CPU ports. The fRCPU includes a insurance display screen Unit (CMU) proposing run-time guidance on the existing SFF with admire ¡°situations of use¡±, e.g. appreciate the FMEA assumptions. It acts as a ¡°checker of the checker¡±. It flags as well surprising SW eventualities (such countless loops) and it allows for dynamic coverage pre-integration analysis on application profiles.

    figure 3 : the IP for insurance policy of CPU

    The insurance policy of alternative sub-methods

    The proposed platform-primarily based know-how is completed through a device manage Unit (fRSCU) amassing and synchronizes all the alarms coming from fRCPU and from the different ¡°remote¡± fault supervisors such for instance fRMEM. Then, based on this counsel, it decides if the system (CPU and peripherals) is in a incorrect state and, based on architectural defense necessities, it performs moves equivalent to flagging the working equipment, forcing some fail-secure hardware configuration and the like. fRSCU is incredibly configurable by means of the person. The different ¡°faraway¡± supervisors are: bus supervisors (fRBUS), including a group of blocks (decoders, arbiters, checkers) monitoring sources and sinks of the bus interconnect; peripheral supervisors (fRPERI), enforcing a ¡°hardware verification component¡±, i.e. a block the place a subset of the protocol checks and assertions used to verify a given interface were translated into hardware constructs. fRCPU, fRMEM, fRBUS and fRPERI speak with the fRSCU via a dedicated on-chip powerful interconnect (fRNET) guaranteeing that suggestions is transferred without errors between the distinctive diagnostic gadgets. It assures as well that safeguard-linked information commute in a separate channel respect mission statistics.

    The proposed platform-based expertise is hardware-centric, i.e. the foremost role is played by way of the hardware supervisors. however, in order to supply the optimal tradeoff between prices and advantages, it includes a collection of SW fRIPs: they are very compact SW constructed-in Self- assessments (BISTs) using HW components guaranteed by means of the HW fRIPs.

    results

    common automobile purposes requiring the maximum defense integrity ranges (SIL2 or SIL3) are passive and energetic defense programs, peculiarly final ones. for example, in ESP (electronic balance program) and EPS (electric vigor guidance), the MCU is playing a crucial role in the guidance and braking manage loop. The identical happens for ACC (Adaptive Cruise control) or ADC (active Dynamic control). For all these capabilities, defense integrity need to be certain and therefore a comprehensive defense-monitoring device is of primary value.

    The least difficult architecture that makes use of the proposed platform-primarily based expertise is a single-CPU asymmetric answer [8], where a common CPU-based microcontroller is complemented by the fRCPU and by way of some situations of alternative fRIPs. consequences of a demonstrator according to PHILIPS SJA2510 microcontroller and on a ARM968ES CPU, show that SIL3 is reachable with this architecture. The fRCPU coverage prices 20%-forty% of CPU gate count (figure four).

    If gadget behaviors are certainly defined or if the utility is mounted, ¡°profiles¡± will also be used so as to add more circumstances to the SRS and therefore to deeply optimize the fRCPU: all the way through construction, by utilizing a SW profiler, it's extracted a profile for the tiers of purposes of interest (e.g. certain facts concerning the guidance used in such functions). This profile is used to customise the SRS and to generate the most excellent HW configuration for the fRCPU. After creation, by using the fRCPU CMU, it is checked if a selected SW software is fully covered by way of the customized fRCPU or not. In case isn¡¯t absolutely lined, by utilizing the SW adapter, the application can also be tailored to cowl such ¡°holes¡±.

    figure 4 : benchmark with twin-core

    Conclusion

    The proposed platform-based technology is relevant for multiprocessors architectures as well. If bigger availability is required, it can also be used to boost lockstep and mutual redundant solutions or other multiprocessors solutions such [9]. In this sort of case, the fRSCU acts just like the comparator of a dual-core method, whereas two fRCPUs (one for every CPU) assure adequate ¡°clues¡± for the fRSCU to determine which of both CPUs is inaccurate in case of a mismatch, enabling a failoperational state.

    In abstract, the proposed platform-based mostly expertise principally aims on the reduction of HW and SW charges mandatory to implement a fault strong MCU in adherence with IEC 61508 SIL3. here is executed by using imposing an optimized HW CPU fault detection, by way of presenting committed HW to replace, guide or supplement SW tests and with the aid of distributing robustness to total SoC. Being platform-primarily based, it pursuits scalability and suppleness as well, via enforcing a portable and reusable architecture.

    References

    [1] H. Tahne, ¡°safe and reputable computer manage: methods ideas and strategies¡±, Mech. Lab, Univ. inventory, 1996

    [2] CEI international general IEC 61508, 1998-2000

    [3] T. Fruehling, ¡°Delphi Secured Microcontroller structure¡±, SAE Technical Paper, 2000-01-1052

    [4] US Patent n.5436837 and n.5880568, and DE Patent n.19933086 by way of Robert Bosch Gmbh

    [5] A. SanGiovanni Vincentelli, ¡°Platform-primarily based Design and utility Design Meth. for Embedded methods¡±, IEEE Design and check, Nov-Dec 2001

    [6] R. Mariani, M. Chiavacci, S. Motto, ¡°dependable microcontroller, formulation for designing a dependable microcontroller and desktop program product therefor¡±, European Patent, EP1496435

    [7] R. Mariani, G. Boschi, ¡°A device stage strategy for Embedded reminiscence Robustness¡± JSSE particular challenge: Papers selected from the 1st overseas convention on memory technology and Design - ICMTD¡¯05

    [8] R. Mariani, P. Fuhrmann, B. Vittorelli, ¡°economical approach to Error Detection for an Embedded automotive Platform¡±, SAE 2006 World Congress & Exhibition, April 2006, Detroit, MI, country

    [9] M. Peri, S. Pezzini, A. Ferrari, A. Sangiovanni-Vincentelli, M. Baleani, ¡°Fault Tolerant platforms for automobile defense vital purposes¡±, instances¡¯03, Oct. 30¨CNov. 2, 2003, San Jose, California




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